1. Field of the Invention
The invention relates to a sample and hold arrangement to sample an input signal comprising at least an operational amplifier having an inverting input, a non-inverting input connected to a reference voltage (or ground) and an output, a first capacitor one side of which may be connected through a first switch to the input voltage, a second capacitor one side of which may be connected to the output of the operational amplifier through a second switch.
2. Description of Related Art
Such an arrangement is known from U.S. Pat No. 4,439,693. The operation of this known arrangement will be first discussed referring to FIGS. 1a and b, which are derive from FIGS. 3a and b of said patent publication. The known arrangement has as an objective to prevent that the offset voltage at the input of the operational amplifier 10 influences the output signal Vout of the sample and hold arrangement. Therefore, the prior art arrangement performs two steps. In the first step (FIG. 1a) the output and the inverting input of the operational amplifier 10 are connected to one another and the resulting offset voltage of the operational amplifier is stored on both the first capacitor Cin and the second capacitor CF. The first capacitor Cin is connected between the inverting input and the input voltage to be sampled, while the second capacitor CF is at that moment connected between the inverting input and the reference voltage (or ground). In the second step the direct connection 44 between the output and the inverting input of the operational amplifier is disconnected and the second capacitor CF is connected between the output and the inverting input of the operational amplifier. Thereby, a voltage of equal magnitude as the offset voltage but having opposite polarity as the original offset voltage is added to the offset voltage present at the input of the operational amplifier, in such a way that the influence of the offset voltage is neutralized.
Consequently, in this prior art arrangement the output voltage of the circuit is made equal to the offset voltage during the compensation phase. Because just before the previous sample is still at the output, the output voltage, therefore, generally has to make a large voltage step. Therefore, higher demands have to be met regarding the rate of the operational amplifier applied. Furthermore, as the output voltage of the prior art circuit is equal to the offset voltage during the compensation phase no continuous-time low pass filter can be applied to reconstruct the original signal. During the compensation phase, however, the output signal is no function of the input signal, so that the output signal of a low pass filter eventually applied would depend substantially on the offset voltage. Therefore, the prior art circuit may be only applied in such cases where the output signal of the sample and hold arrangement is only processed in a discrete-time way and the magnitude of the output signal during the compensation phase is of no significance.
Moreover, in the prior art circuit the accuracy depends on the extent to which the two capacitors are similar to one another. An accuracy of 0.01% is claimed, however, because of the more limited relative matching of capacitors on a chip (typical value 0.1%) this must be worse.